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| a FEATURES Low Offset Voltage: 50 V max Low Noise Voltage at 100 Hz, 1 mA: 1.0 nV/Hz max High Gain (hFE): 500 min at I C = 1 mA 300 min at IC = 1 A Excellent Log Conformance: rBE 0.3 Low Offset Voltage Drift: 0.1 V/ C max Improved Direct Replacement for LM194/394 Available in Die Form Low Noise, Matched Dual Monolithic Transistor MAT02 PIN CONNECTION TO-78 (H Suffix) NOTE Substrate is connected to case on TO-78 package. Substrate is normally connected to the most negative circuit potential, but can be floated. PRODUCT DESCRIPTION ABSOLUTE MAXIMUM RATINGS 1 The design of the MAT02 series of NPN dual monolithic transistors is optimized for very low noise, low drift, and low rBE. Precision Monolithics' exclusive Silicon Nitride "TriplePassivation" process stabilizes the critical device parameters over wide ranges of temperature and elapsed time. Also, the high current gain (hFE) of the MAT02 is maintained over a wide range of collector current. Exceptional characteristics of the MAT02 include offset voltage of 50 V max (A/E grades) and 150 V max F grade. Device performance is specified over the full military temperature range as well as at 25C. Input protection diodes are provided across the emitter-base junctions to prevent degradation of the device characteristics due to reverse-biased emitter current. The substrate is clamped to the most negative emitter by the parasitic isolation junction created by the protection diodes. This results in complete isolation between the transistors. The MAT02 should be used in any application where low noise is a priority. The MAT02 can be used as an input stage to make an amplifier with noise voltage of less than 1.0 nV/Hz at 100 Hz. Other applications, such as log/antilog circuits, may use the excellent logging conformity of the MAT02. Typical bulk resistance is only 0.3 to 0.4 . The MAT02 electrical characteristics approach those of an ideal transistor when operated over a collector current range of 1 A to 10 mA. For applications requiring multiple devices see MAT04 Quad Matched Transistor data sheet. Collector-Base Voltage (BVCBO) . . . . . . . . . . . . . . . . . . . . 40 V Collector-Emitter Voltage (BVCEO) . . . . . . . . . . . . . . . . . . 40 V Collector-Collector Voltage (BVCC) . . . . . . . . . . . . . . . . . . 40 V Emitter-Emitter Voltage (BVEE) . . . . . . . . . . . . . . . . . . . . . 40 V Collector Current (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Emitter Current (IE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Total Power Dissipation Case Temperature 40C2 . . . . . . . . . . . . . . . . . . . . . 1.8 W Ambient Temperature 70C3 . . . . . . . . . . . . . . . . 500 mW Operating Temperature Range MAT02A . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C MAT02E, F . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C Operating Junction Temperature . . . . . . . . . . -55C to +150C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300C Junction Temperature . . . . . . . . . . . . . . . . . . -65C to +150C NOTES 1 Absolute maximum ratings apply to both DICE and packaged devices. 2 Rating applies to applications using heat sinking to control case temperature. Derate linearly at 16.4 mW/C for case temperature above 40C. 3 Rating applies to applications not using a heat sinking; devices in free air only. Derate linearly at 6.3 mW/C for ambient temperature above 70C. ORDERING GUIDE1 Model MAT02AH2 MAT02EH MAT02FH VOS max Temperature (TA = +25 C) Range 50 V 50 V 150 V -55C to +125C -55C to +125C -55C to +125C Package Option TO-78 TO-78 TO-78 NOTES 1 Burn-in is available on commercial and industrial temperature range parts in TO-can packages. 2 For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 MAT02-SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V Parameter Current Gain Symbol hFE CB = 15 V, IC = 10 A, TA = 25 C, unless otherwise noted.) MAT02A/E Min Typ Max 500 500 400 300 605 590 550 485 0.5 10 10 10 5 5 30 0.3 25 35 35 1.6 0.9 0.85 0.85 0.05 Min 400 400 300 200 2 50 25 25 25 25 70 0.5 200 200 200 2 1 1 1 0.1 25 0.6 40 200 23 35 200 23 35 MAT02F Typ Max 605 590 550 485 0.5 80 10 10 5 5 30 0.3 25 35 35 1.6 0.9 0.85 0.85 0.05 Units Conditions IC = 1 mA1 IC = 100 A IC = 10 A IC = 1 A 10 A IC 1 mA2 VCB = 0, 1 A IC 1 mA3 0 VCB VMAX,4 1 A IC 1 mA3 VCB = 0 V 1 A IC 1 mA3 0 VCB VMAX 10 A IC 10 mA5 VCB = VMAX VCC = VMAX5, 6 VCE = VMAX5, 6 VBE = 0 IC = 1 mA, VCB = 07 fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz IC = 1 mA, IB = 100 A IC = 10 A IC = 10 A Current Gain Match Offset Voltage Offset Voltage Change vs. VCB Offset Voltage Change vs. Collector Current Offset Current Change vs. VCB Bulk Resistance Collector-Base Leakage Current Collector-Collector Leakage Current Collector-Emitter Leakage Current Noise Voltage Density hFE VOS VOS/VCB VOS/IC IOS/VCB rBE ICBO ICC ICES en 4 150 50 50 50 50 70 0.5 400 400 400 3 2 2 2 0.2 34 1.3 % V V V V V pA/V pA pA pA nV/Hz nV/Hz nV/Hz nV/Hz V nA nA V MHz pF pF Collector Saturation Voltage Input Bias Current Input Offset Current Breakdown Voltage Gain-Bandwidth Product Output Capacitance Collector-Collector Capacitance VCE(SAT) IB IOS BVCEO fT COB CCC 40 IC = 10 mA, VCE = 10 V VCB = 15 V, IE = 0 VCC = 0 NOTES 1 Current gain is guaranteed with Collector-Base Voltage (V CB) swept from 0 to V MAX at the indicated collector currents. 100 (IB) (hFE min) 2 Current gain match (hFE) is defined as: hFE = IC 3 Measured at IC = 10 A and guaranteed by design over the specified range of I C. 4 This is the maximum change in V OS as VCB is swept from 0 V to 40 V. 5 Guaranteed by design. 6 ICC and ICES are verified by measurement of I CBO. 7 Sample tested. Specifications subject to change without notice. -2- REV. C MAT02 ELECTRICAL CHARACTERISTICS (V Parameter Symbol Conditions CB = 15 V, -25 C TA +85 C, unless otherwise noted.) MAT02E Min Typ Max MAT02F Min Typ Max Units Offset Voltage Average Offset Voltage Drift Input Offset Current Input Offset Current Drift Input Bias Current Current Gain VOS TCVOS IOS TCIOS IB hFE VCB = 0 1 A IC 1 mA1 10 A IC 1 mA, 0 VCB VMAX2 VOS Trimmed to Zero3 IC = 10 A IC = 10 A4 IC = 10 A IC = 1 mA5 IC = 100 A IC = 10 A IC = 1 A VCB = VMAX VCE = VMAX, VBE = 0 VCC = VMAX 70 220 V V/C nA pA/C nA 0.08 0.3 0.03 0.1 8 40 325 275 225 200 2 3 3 90 45 300 250 200 150 0.08 1 0.03 0.3 13 40 150 50 Collector-Base Leakage Current Collector-Emitter Leakage Current Collector-Collector Leakage Current ICBO ICES ICC 3 4 4 nA nA nA ELECTRICAL CHARACTERISTICS (V Parameter Symbol CB = 15 V, -55 C TA +125 C, unless otherwise noted.) Min MAT02A Typ Max Units Conditions Offset Voltage Average Offset Voltage Drift Input Offset Current Input Offset Current Drift Input Bias Current Current Gain VOS TCVOS IOS TCIOS IB hFE VCB = 0 1 A IC 1 mA1 10 A IC 1 mA, 0 VCB VMAX2 VOS Trimmed to Zero3 IC = 10 A IC = 10 A4 IC = 10 A IC = 1 mA5 IC = 100 A IC = 10 A IC = 1 A VCB = VMAX TA = 125C VCE = VMAX, VBE = 0 TA = 125C VCC = VMAX TA = 125C 0.08 0.03 80 V V/C V/C nA pA/C nA 0.3 0.1 9 90 60 40 275 225 125 150 15 50 30 Collector-Base Leakage Current Collector-Emitter Leakage Current Collector-Collector Leakage Current ICBO ICES ICC nA nA nA NOTES 1 Measured at IC = 10 A and guaranteed by design over the specified range of I C. 2 3 Guaranteed by V OS test (TCVOS V OS for VOS T VBE) T = 298K for TA = 25C. The initial zero offset voltage is established by adjusting the ratio of IC1 to IC2 at T A = 25C. This ratio must be held to 0.003% over the entire temperature range. Measurements are taken at the temperature extremes and 25 C. 4 Guaranteed by design. 5 Current gain is guaranteed with Collector-Base Voltage (V CB) swept from 0 to V MAX at the indicated collector current. Specifications subject to change without notice. REV. C -3- MAT02 WAFER TEST LIMITS (@ 25 C for V Parameter CB = 15 V and IC = 10 A, unless otherwise noted.) Conditions MAT02N Limits Units Symbol Breakdown Voltage Offset Voltage Input Offset Current Input Bias Current Current Gain Current Gain Match Offset Voltage Change vs. VCB Offset Voltage Change vs. Collector Current Bulk Resistance Collector Saturation Voltage BVCEO VOS IOS IB hFE hFE VOS/VCB VOS/IC rBE VCE (SAT) 10 A IC 1 mA1 VCB = 0 V IC = 1 mA, VCB = 0 V IC = 10 A, VCB = 0 V 10 A IC 1 mA, VCB = 0 V 0 V VCB 40 V 10 A IC 1 mA1 VCB = 0 10 A IC 1 mA1 100 A IC 10 mA IC = 1 mA IB = 100 A 40 150 1.2 34 400 300 4 50 50 0.5 0.2 V min V max nA max nA max min % max V max V max max V max NOTES 1 Measured at lC = 10 A and guaranteed by design over the specified range of I C. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. TYPICAL ELECTRICAL CHARACTERISTICS (V Parameter Symbol CB = 15 V, IC = 10 A, TA = +25 C, unless otherwise noted.) MAT02N Limits Units Conditions Average Offset Voltage Drift Average Offset Current Drift Gain-Bandwidth Product Offset Current Change vs. VCB TCVOS TCIOS fT IOS/VCB 10 A IC 1 mA 0 VCB VMAX IC = 10 A VCE = 10 V, IC = 10 mA 0 VCB 40 V 0.08 40 200 70 V/C pA/C MHz pA/V DICE CHARACTERISTICS 1. COLLECTOR (1) 2. BASE (1) 3. EMITTER (1) 4. COLLECTOR (2) 5. BASE (2) 6. EMITTER (2) 7. SUBSTRATE Die Size 0.061 x 0.057 inch, 3,477 sq. mils (1.549 x 1.448 mm, 224 sq. mm) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the MAT02 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. C MAT02 Figure 1. Current Gain vs. Collector Current Figure 2. Current Gain vs. Temperature Figure 3. Gain Bandwidth vs. Collector Current Figure 4. Base-Emitter-On Voltage vs. Collector Current Figure 5. Small Signal Input Resistance vs. Collector Current Figure 6. Small-Signal Output Conductance vs. Collector Current Figure 7. Saturation Voltage vs. Collector Current Figure 8. Noise Voltage Density vs. Frequency Figure 9. Noise Voltage Density vs. Collector Current REV. C -5- MAT02 Figure 10. Noise Current Density vs. Frequency Figure 11. Total Noise vs. Collective Current Figure 12. Collector-to-Base Leakage vs. Temperature Figure 13. Collector-to-Collector Leakage vs. Temperature Figure 14. Collector-to-Collector Capacitance vs. Collector-to Substrate Voltage Figure 15. Collector-Base Capacitance vs. Reverse Bias Voltage Figure 16. Collector-to-Collector Capacitance vs. Reverse Bias Voltage Figure 17. Emitter-Base Capacitance vs. Reverse Bias Voltage -6- REV. C MAT02 Figure 18. Log Conformance Test Circuit LOG CONFORMANCE TESTING The log conformance of the MAT02 is tested using the circuit shown above. The circuit employs a dual transdiode logarithmic converter operating at a fixed ratio of collector currents that are swept over a 10:1 range. The output of each transdiode converter is the VBE of the transistor plus an error term which is the product of the collector current and rBE, the bulk emitter resistance. The difference of the VBE is amplified at a gain of x100 by the AMP01 instrumentation amplifier. The differential emitter-base voltage (VBE) consists of a temperaturedependent dc level plus an ac error voltage which is the deviation from true log conformity as the collector currents vary. The output of the transdiode logarithmic converter comes from the idealized intrinsic transistor equation (for silicon): VBE kT I C In = where IS q An error term must be added to this equation to allow for the bulk resistance (rBE) of the transistor. Error due to the op amp input current is limited by use of the OP15 BiFET-input op amp. The resulting AMP01 input is: C1 VBE = q In I + IC1 rBE1 - IC2 rBE2 C2 kT I (2) A ramp function which sweeps from 1 V to 10 V is converted by the op amps to a collector current ramp through each transistor. Because IC1 is made equal to 10 IC2, and assuming TA = 25C, the previous equation becomes: VBE = 59 mV + 0.9 IC1 rBE (rBE ~ 0) As viewed on an oscilloscope, the change in VBE for a 10:1 change in IC is then displayed as shown below: (1) k = Boltzmann's Constant (1.38062 x 10-23 J/K) q = Unit Electron Charge (1.60219 x 10-19 C) T = Absolute Temperature, K (= C + 273.2) IS = Extrapolated Current for VBE0 IC = Collector Current REV. C -7- MAT02 With the oscilloscope ac coupled, the temperature dependent term becomes a dc offset and the trace represents the deviation from true log conformity. The bulk resistance can be calculated from the voltage deviation VO and the change in collector current (9 mA): rBE V O 1 x = 9 mA 100 by various offsetting techniques. Protective diodes across each base-to-emitter junction would normally be needed, but these diodes are built into the MAT02. External protection diodes are therefore not needed. For the circuit shown in Figure 19, the operational amplifiers make I1 = VX/R1, I2 = VY/R2, I3 = VZ/R3, and IO = VO/RO. The output voltage for this one-quadrant, log-antilog multiplier/divider is ideally: VO = R3RO V XV Y (VX, VY, VZ > 0) R1R2 V Z (3) This procedure finds rBE for Side A. Switching R1 and R2 will provide the rBE for Side B. Differential rBE is found by making R1 = R2. (4) APPLICATIONS: NONLINEAR FUNCTIONS MULTIPLIER/DIVIDER CIRCUIT The excellent log conformity of the MAT02 over a very wide range of collector current makes it ideal for use in log-antilog circuits. Such nonlinear functions as multiplying, dividing, squaring, and square-rooting are accurately and easily implemented with a log-antilog circuit using two MAT02 pairs (see Figure 19). The transistor circuit accepts three input currents (I1, I2, and I3) and provides an output current IO according to IO = I1I2/I3. All four currents must be positive in the log-antilog circuit, but negative input voltages can be easily accommodated If all the resistors (RO, R1, R2, R3) are made equal, then VO = VXVY/VZ. Resistor values of 50 k to 100 k are recommended assuming an input range of 0.1 V to +10 V. ERROR ANALYSIS The base-to-emitter voltage of the MAT02 in its forward active operation is: VBE = kT I C In + rBEIC, VCB ~ 0 IS q (5) The first term comes from the idealized intrinsic transistor equation previously discussed (see equation (1)). Figure 19. One-Quadrant Multiplier/Divider -8- REV. C MAT02 approximately 26 mV and the error due to an rBEIC term will be rBEIC/26 mV. Using an rBE of 0.4 for the MAT02 and assuming a collector current range of up to 200 A, then a peak error of 0.3% could be expected for an rBEIC error term when using the MAT02. Total error is dependent on the specific application configuration (multiply, divide, square, etc.) and the required dynamic range. An obvious way to reduce ICrBE error is to reduce the maximum collector current, but then op amp offsets and leakage currents become a limiting factor at low input levels. A design range of no greater than 10 A to 1 mA is generally recommended for most nonlinear function circuits. Figure 20. Compensation of Bulk Resistance Error Extrinsic resistive terms and the early effect cause departure from the ideal logarithmic relationship. For small VCB, all of these effects can be lumped together as a total effective bulk resistance rBE. The rBEIC term causes departure from the desired logarithmic relationship. The rBE term for the MAT02 is less than 0.5 and rBE between the two sides is negligible. Returning to the multiplier/divider circuit of Figure 1 and using Equation (4): VBE1A + VBE2A - VBE2B -VBE1B + (I1 + I2 - IO - I3) rBE = 0 If the transistor pairs are held to the same temperature, then: kT II kT I S1AI S2A In 1 2 = In + (I1 + I2 - IO - I3) rBE I 3IO q I S1B I S2B q A powerful technique for reducing error due to ICrBE is shown in Figure 20. A small voltage equal to ICrBE is applied to the transistor base. For this circuit: VB = RC r BE V and ICrBE = V R2 1 R1 1 (10) The error from rBEIC is cancelled if RC/R2 is made equal to rBE/ R1. Since the MAT02 bulk resistance is approximately 0.39 , an RC of 3.9 and R2 of 10 R1 will give good error cancellation. In more complex circuits, such as the circuit in Figure 19, it may be inconvenient to apply a compensation voltage to each individual base. A better approach is to sum all compensation to the bases of Q1. The "A" side needs a base voltage of (VO/RO + VZ/R3) rBE and the "B" side needs a base voltage of (VX/R1+VY/ R2) rBE. Linearity of better than 0.1% is readily achievable with this compensation technique. Operational amplifier offsets are another source of error. In Figure 20, the input offset voltage and input bias current will cause an error in collector current of (VOS/R1) + IB. A low offset op amp, such as the OP07 with less than 75 V of VOS and IB of less than 3 nA, is recommended. The OP22/OP32, a programmable micropower op amp, should be considered if low power consumption or single-supply operation is needed. The value of frequency-compensating capacitor (CO) is dependent on the op amp frequency response and peak collector current. Typical values for CO range from 30 pF to 300 pF. ... FOUR-QUADRANT MULTIPLIER (6) If all the terms on the right-hand side were zero, then we would have In (I1 I2/I3 IO) equal to zero which would lead directly to the desired result: IO = I1I 2 , where I1, I2, I3, IO > 0 I3 (7) Note that this relationship is temperature independent. The right-hand side of Equation (6) is near zero and the output current IO will be approximately I1 I2/I3. To estimate error, define o as the right-hand side terms of Equation (6): o = In I S1AI S2A q + (I + I2 - IO - I3) rBE I S1B I S2B kT 1 (8) For the MAT02, In (ISA/ISB) and ICrBE are very small. For small o, O ~ 1 + o and therefore: I1I 2 =1+o I 3IO A simplified schematic for a four-quadrant log/antilog multiplier is shown in Figure 21. As with the previously discussed onequadrant multiplier, the circuit makes IO = I1 I2/I3. The two input currents, I1 and I2, are each offset in the positive direction. This positive offset is then subtracted out at the output stage. Assuming ideal op amps, the currents are: I1 = VX VR V V + ,I = Y + R R1 R2 2 R1 R2 (9) IO ~ I1I2 (1 - o) I3 IO = V X VY V R V O V + + + ,I = R R1 R1 R2 RO 3 R2 (11) The In (ISA/ISB) terms in o cause a fixed gain error of less than 0.6% from each pair when using the MAT02, and this gain error is easily trimmed out by varying RO. The ICrBE terms are more troublesome because they vary with signal levels and are multiplied by absolute temperature. At 25C, kT/q is From IO = I1 I2/I3, the output voltage will be: VO = RO R2 V XV Y 2 VR R1 (12) REV. C -9- MAT02 Collector-current range is the key design decision. The inherently low rBE of the MAT02 allows the use of a relatively high collector current. For input scaling of 10 V full-scale and using a 10 V reference, we have a collector-current range for I1 and I2 of: -10 10 10 10 R + R IC R + R 1 1 2 2 MULTIFUNCTION CONVERTER The multifunction converter circuit provides an accurate means of squaring, square rooting, and of raising ratios to arbitrary powers. The excellent log conformity of the MAT02 allows a wide range of exponents. The general transfer function is: V Z VO = VY V X m (13) (15) Practical values for R1 and R2 would range from 50 k to 100 k. Choosing an R1 of 82 k and R2 of 62 k provides a collector-current range of approximately 39 A to 283 A. An RO of 108 k will then make the output scale factor 1/10 and VO = VXVY/10. The output, as well as both inputs, are scaled for 10 V full scale. Linear error for this circuit is substantially improved by the small correction voltage applied to the base of Q1 as shown in Figure 21. Assuming an equal bulk emitter resistance for each MAT02 transistor, then the error is nulled if: (I1 + I2 - I3 - IO) rBE + VO = 0 The currents are known from the previous discussion, and the relationship needed is simply: VO = r BE V RO O VX, VY, and VZ are input voltages and the exponent "m" has a practical range of approximately 0.2 to 5. Inputs VX and VY are often taken from a fixed reference voltage. With a REF01 providing a precision +10 V to both VX and VY, the transfer function would simplify to: V Z VO = 10 10 m (16) As with the multiplier/divider circuits, assume that the transistor pairs have excellent matching and are at the same temperature. The In ISA/ISB will then be zero. In the circuit of Figure 22, the voltage drops across the base-emitter junctions of Q1 provide: RB kT I V= In Z RB + KR A A q IX (14) (17) The output voltage is attenuated by a factor of rBE/RO and applied to the base of Q1 to cancel the summation of voltage drops due to rBEIC terms. This will make In (I1 I2/I3 IO) more nearly zero which will thereby make IO = I1 I2/I3 a more accurate relationship. Linearity of better than 0.1% is readily achievable with this circuit if the MAT02 pairs are carefully kept at the same temperature. IZ is VZ/R1 and IX is VX/R1. Similarly, the relationship for Q2 is: RB kT I VA = In O IY q RB + (1 - K )RA (18) IO is VO/RO and IY is VY/R1. These equations for Q1 and Q2 can then be combined. RB + KR A I I In Z = In O IX IY RB + (1 - K )RA (19) Figure 21. Four-Quadrant Multiplier -10- REV. C MAT02 Substituting in the voltage relationships and simplifying leads to: V Z RO VO = R V Y V , where X 1 m (20) RB + KR A m = R + 1- K R )A B( Accuracy is limited at the higher input levels by bulk emitter resistance, but this is much lower for the MAT02 than for other transistor pairs. Accuracy at the lower signal levels primarily depends on the op amp offsets. Accuracies of better than 1% are readily achievable with this circuit configuration and can be better than 0.1% over a limited operating range. FAST LOGARITHMIC AMPLIFIER The factor "K" is a potentiometer position and varies from zero to 1.0, so "m" ranges from RB/(RA + RB) to (RB + RA)/RB. Practical values are 125 for RB and 500 for RA; these values will provide an adjustment range of 0.2 to 5.0. A value of 100 k is recommended for the R1 resistors assuming a fullscale input range of 10 V. As with the one-quadrant multiplier/ divider circuit previously discussed, the VX, VY, and VZ inputs must all be positive. The op amps should have the lowest possible input offsets. The OP07 is recommended for most applications, although such programmable micropower op amps as the OP22 or OP32 offer advantages in low-power or single-supply circuits. The micropower op amps also have very low input bias-current drift, an important advantage in log/antilog circuits. External offset nulling may be needed, particularly for applications requiring a wide dynamic range. Frequency compensating capacitors, on the order of 50 pF, may be required for A2 and A3. Amplifier A1 is likely to need a larger capacitor, typically 0.0047 F, to assure stability. The circuit of Figure 23 is a modification of a standard logarithmic amplifier configuration. Running the MAT02 at 2.5 mA per side (full-scale) allows a fast response with wide dynamic range. The circuit has a 7 decade current range, a 5 decade voltage range, and is capable of 2.5 s settling time to 1% with a 1 V to 10 V step. The output follows the equation: VO = R3 + R2 kT V REF In R2 V IN q (21) The output is inverted with respect to the input, and is nominally -1 V/decade using the component values indicated. LOW-NOISE 1000 AMPLIFIER The MAT02 noise voltage is exceptionally low, only 1 nV/Hz at 10 Hz when operated over a collector-current range of 1 mA to 4 mA. A single-ended x1000 amplifier that takes advantage of this low MAT02 noise level is shown in Figure 24. In addition to low noise, the amplifier has very low drift and high CMRR. An OP32 programmable low-power op amp is used for the second stage to obtain good speed with minimal power consumption. Small-signal bandwidth is 1 MHz, slew rate is 2.4 V/s, and total supply current is approximately 2.8 mA. Figure 22. Multifunction Converter REV. C -11- MAT02 Transistors Q2 and Q3 form a 2 mA current source (0.65 V/ 330 ~ 2 mA). Each collector of Q1 operates at 1 mA. The OP32 inputs are 3 V below the positive supply voltage (RLIC ~ 3 V). The OP32's low input offset current, typically less than 1 nA, and low offset voltage of 1 mV cause negligible error when referred to the amplifier input. Input stage gain is gmRL, which is approximately 100 when operating at IC of 1 mA with RL of 3 k. Since the OP32 has a minimum open-loop gain of 500,000, total open-loop gain for the composite amplifier is over 50 million. Even at closed-loop gain of 1000, the gain error due to finite open-loop gain will be negligible. The OP32 features excellent symmetry of slew-rate and very linear gain. Signal distortion is minimal. Frequency compensation is very easy with this circuit; just vary the set-resistor RS for the desired frequency response. Gain-bandwidth of the OP32 varies directly with the supply current. A set resistor of 549 k was found to provide the best step response for this circuit. The resultant supply current is found from: RSET = (V +) - (V -) - (2V BE ), I I SET SY =15 I SET (22) 000000000 PRINTED IN U.S.A. The ISET, using 15 V supplies and an RSET of 549 k, is approximately 52 A which will result in supply current of 784 A. Dynamic range of this amplifier is excellent; the OP32 has an output voltage swing of 14 V with a 15 V supply. Input characteristics are outstanding. The MAT02F has offset voltage of less than 150 V at 25C and a maximum offset drift of 1 V/C. Nulling the offset will further reduce offset drift. This can be accomplished by slightly unbalancing the collector load resistors. This adjustment will reduce the drift to less than 0.1 V/C. Input bias current is relatively low due to the high current gain of the MAT02. The minimum of 400 at 1 mA for the MAT02F implies an input bias current of approximately 2.5 A. This circuit should be used with signals having relatively low source impedance. A high source impedance will degrade offset and noise performance. This circuit configuration provides exceptionally low input noise voltage and low drift. Noise can be reduced even further by raising the collector currents from 1 mA to 3 mA, but power consumption is then increased. OUTLINE DIMENSION Dimensions shown in inches and (mm). 6-Lead Metal Can (TO-78) REFERENCE PLANE 0.750 (19.05) 0.500 (12.70) 0.250 (6.35) MIN 0.050 (1.27) MAX 4 0.370 (9.40) 0.335 (8.51) 0.335 (8.51) 0.305 (7.75) Figure 23. Fast Logarithmic Amplifier 0.185 (4.70) 0.165 (4.19) 0.100 (2.54) BSC 0.160 (4.06) 0.110 (2.79) 5 0.200 (5.08) BSC 3 2 6 0.045 (1.14) 0.027 (0.69) 0.019 (0.48) 0.016 (0.41) 0.040 (1.02) MAX 0.045 (1.14) 0.010 (0.25) 0.021 (0.53) 0.016 (0.41) 0.100 (2.54) BSC 1 0.034 (0.86) 0.027 (0.69) 45 BSC BASE & SEATING PLANE Figure 24. Low-Noise, Single-Ended X1000 Amplifier -12- REV. C |
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